Generally speaking, a PLL mainly comprises a phase detector, a charge pump, a loop filter and a voltage controlled oscillator (VCO). In practice, the PLL is widely applied to electronic and communication products, e.g., memories, microprocessors, hard disk driving apparatuses, radio frequency (RF) transceivers, and fiber optic transceivers.
FIG. 1 shows a block diagram of a conventional frequency calibration apparatus applied to a PLL. A frequency calibration apparatus 1 comprises a frequency detecting module 10 and a state machine 12. The frequency detecting module 10 comprises a multiplier 100, a first counter 102, a second counter 104 and a comparing unit 106. The multiplier 100 is coupled to the first counter 102; the first counter 102 and the second counter 104 are coupled to the comparing unit 106; and the comparing unit 106 is coupled to the state machine 12. A reference clock CKR entering the frequency calibration apparatus 1 is generated from dividing a reference frequency by a reference frequency divider. A feedback clock CKV entering the frequency calibration apparatus 1 is generated from dividing an output frequency of a VCO of the PLL by a main frequency divider.
When the low-speed reference clock CKR enters the frequency calibration apparatus 1, the multiplier 100 multiplies the low-speed reference clock CKR by a constant to generate a high-speed clock MCKR. After that, the first counter 102 generates a first count according to the high-speed clock MCKR. When the high-speed feedback clock CKV enters the frequency calibration apparatus 1, the second counter 104 directly generates a second count according to the feedback clock CKV. It is to be noted that the first counter 102 and the second counter 104 are operated with a high-speed as well.
The comparing unit 106 receives the first count and the second count from the first counter 102 and the second counter 104, respectively, and compares the first count with the second count to generate a comparison result indicating that the second count is greater or smaller than the first count. After that, the state machine 12 selects an optimal frequency curve and calibrates the output frequency of the VCO of the PLL according to the optimal frequency curve. It is to be noted that, the frequency calibration apparatus 1 iterates the foregoing frequency calibration procedure to the PLL in a frequency locked mode until a ratio of the calibrated output frequency and the reference frequency approximates a predetermined ratio. Further, monitoring periods applied every time the calibration procedure is iterated are the same length.
In conclusion, the conventional calibration apparatus 1 still has numerous disadvantages to be overcome. For example, since the conventional frequency calibration apparatus 1 adopts a low-speed reference clock CKR and a same monitoring period in every calibration procedure, an overall calibration time for calibrating the output frequency of the PLL by the conventional frequency calibration apparatus 1 is long. In addition, the frequency calibration apparatus 1 first applies the multiplier 100 to process the low-speed reference clock CKR, and then applies the first counter 102 to generate the first count according to the high-speed clock MCKR, such that not only the first counter 102 and the second counter 104 need to be operated with the high-speed, but also cost of the frequency calibration apparatus 1 is additionally increased due to the multiplier 100.
Therefore, a main object of the present disclosure is to provide a frequency calibration apparatus applied to a PLL and an operating method thereof to solve the foregoing issues.